1. Field of the Invention
The present invention relates to a head substrate, printhead, and head cartridge. Particularly, the present invention relates to a head substrate obtained by forming, on a single substrate, electrothermal transducers for generating heat energy necessary to print, and switching elements for driving the electrothermal transducers, a printhead using the head substrate, and a head cartridge using the printhead.
2. Description of the Related Art
Conventionally, the electrothermal transducer (heater) of an inkjet printhead and a switching element for switching a heater to be driven are formed on a single substrate using a semiconductor process technique, as disclosed in the U.S. Pat. No. 6,290,334. Many proposals have been made for a layout arrangement in which heaters and switching elements are integrated on a head substrate. When an NMOS transistor is employed as a switching element, a level converter (LVC) is integrated on a head substrate to boost a VDD voltage serving as the power supply voltage of a logic circuit in order to improve the drivability of the NMOS transistor. As the arrangement of an LVC array, an arrangement disclosed in the U.S. Pat. No. 6,302,504 is known. Other arrangements of the level converter are one in the United States Patent Publication No. 2006/0139412 and one in Japanese Patent Laid-Open No. 2005-169868.
FIG. 13 is a circuit diagram showing an example of an equivalent circuit including a heater 203 and driver transistor 204.
A logic circuit such as a shift register (S/R) (not shown) or a decoder (not shown) processes a heater driving signal. The processed signal is output with the amplitude of a logic voltage (VDD voltage) of about 3.3 V from an AND gate 206 serving as the final stage of the logic circuit. For illustrative convenience, an output from the logic circuit is expressed as an output from the AND gate in FIG. 13. A level converter 205 converts the output signal from the AND gate to have the amplitude of the second power supply voltage VHT higher than the VDD voltage. This output voltage drives the gate of the driver transistor 204 serving as a switching element for driving a heater.
The effective resistance of the driver transistor in driving the heater 203 is reduced by driving the gate of the driver transistor 204 by a voltage higher than the VDD voltage.
In FIG. 13, a plurality of circuit blocks 210 each having an array of identical circuits are arranged. Many printing elements and switching elements for them are formed on a single substrate.
FIG. 14 is a circuit diagram showing an example of the conventional level converter 205.
In FIG. 14, reference numerals 301a to 301j denote elements which constitute the level converter. More specifically, an IN terminal 301a receives a signal from the logic circuit formed from an element driving signal circuit (not shown), a block selection circuit (not shown), or the like. An inverter 301b receives a signal from the IN terminal 301a and outputs the inverted signal. MOS transistors 301c to 301h constitute a level converter for converting the voltage amplitude of a signal. An inverter 301i buffers an output signal from the level converter. An OUT terminal 301j outputs a level-converted signal.
A signal input to the IN terminal 301a is input to the gates of the PMOS transistor 301g and NMOS transistor 301f, and the inverter 301b. The signal inverted by the inverter 301b is input to the gates of the PMOS transistor 301d and NMOS transistor 301c. Note that the amplitude voltage of an input signal applied to the IN terminal 301a and that of an output signal from the inverter 301b are the VDD voltage.
A circuit operation when a signal input to the IN terminal 301a is at high level (H) (=VDD voltage) will be explained.
The inverted signal of an input signal is applied to the gates of the MOS transistors 301c and 301d, so a low-level (L) voltage (=0 V) is applied. To the contrary, the input signal is directly applied to the gates of the NMOS transistor 301f and PMOS transistor 301g, so a high-level (H) voltage is applied. At this time, the NMOS transistor 301f is turned on. The drain terminal of the NMOS transistor 301f is connected to GND at low impedance.
As shown in FIG. 14, the drain terminal of the NMOS transistor 301f is connected to the gate of the PMOS transistor 301e. The gate of the PMOS transistor 301e is connected to GND at low impedance to turn on the PMOS transistor 301e. In contrast, the gate of the PMOS transistor 301d series-connected to the PMOS transistor 301e receives an output from the inverter 301b, and the gate voltage is set to 0 V. At this time, the PMOS transistor 301e is ON, and the source potential of the PMOS transistor 301d is a VHT voltage higher than the VDD voltage. For this reason, the PMOS transistor 301d is turned on regardless of whether the VDD voltage or 0 V is applied.
The gate voltage of the NMOS transistor 301c series-connected to the PMOS transistor 301d is 0 V, so the NMOS transistor 301c is turned off. The PMOS transistors 301e and 301d are turned on, and the NMOS transistor 301c is turned off. As a result, the potential at the node to which the drains of the PMOS transistor 301d and NMOS transistor 301c are connected and which is connected to the gate of the PMOS transistor 301h changes to VHT serving as the power supply potential of the level converter.
Then, the PMOS transistor 301h is turned off. Since the PMOS transistor 301h is turned off, the NMOS transistor 301f is turned on. The voltage at the node to which the drains of the PMOS transistor 301g and NMOS transistor 301f are connected and which is connected to the gate of the PMOS transistor 301e is finalized at 0 V. The potential at this node is input to the inverter 301i, and an output signal from the inverter 301i serves as an output signal from the level converter. Since the signal input to the inverter 301i has 0 V, the output signal changes to high level, and the VHT voltage is output to the OUT terminal 301j. 
To the contrary, in a circuit operation when a signal input to the IN terminal 301a is at low level (0 V), all the logic values are inverted to output 0 V to the OUT terminal.
FIG. 15 is a timing chart including the input signal of the level converter and the gate voltage of the driver transistor at the heater driving timing of a conventional head substrate.
An output pulse HEAT from a logic circuit 206 which defines the timing to energize the heater 203 is applied to the IN terminal of the level converter 205 with an amplitude of 0 V to the VDD voltage.
In response to the timing of the output pulse HEAT, a current IHT consumed by the driving power supply of the driver transistor 204 transiently flows at the leading and trailing edge timings of the output pulse HEAT. A driver transistor 204 corresponding to a heater 203 selected to be driven is connected to the output of the level converter 205, and receives a signal VG_on with an amplitude of 0 V to the VHT voltage. That is, the signal VG_on is a signal obtained by converting the level of the pulse signal HEAT.
Upon receiving the signal VG_on, the driver transistor 204 keeps ON while a gate voltage equal to or higher than a threshold Vth is applied, and a current IH_on flows through the heater 203. To the contrary, a signal VG_off (=0 V) is applied to a driver transistor 204 corresponding to an unselected heater 203, and no heater current flows. In FIG. 15, a current IH_off represents this.
Recently, an inkjet printing apparatus having a printhead using the above-described head substrate is enhancing the density of nozzles for discharging ink. This means arranging heaters at high density. For this purpose, corresponding driver transistors, level converters (LVCs), and logic circuits need to be arranged at high density. To deal with the recent enhancement in nozzle density, circuits must be arranged at pitches of about ten-odd to several tens of μm. As for the logic circuit, we can cope with the high-density arrangement by miniaturizing a circuit manufactured by a semiconductor manufacturing process, to some extent.
However, a circuit such as a level converter which needs to operate at a voltage higher than the logic voltage must employ a high-voltage tolerant element structure because it needs to assure a tolerable level against a high voltage. However, there is a limit on integrating high-voltage tolerant element structures by the miniaturization process, and it is difficult to arrange them at high density.
Since an attempt to miniaturize devices is difficult, an approach to increasing the density by reducing the number of elements (number of transistors) may be considered.
A transistor serving as a building component of a conventional level converter is necessary to cut off, after switching, a current flowing through the level converter. If the number of transistors decreases, the current keeps flowing depending on the logic state. As a result, the level converter consumes an enormous amount of current.
FIG. 16 is a circuit diagram showing the principle circuit arrangement of a level converter in which an NMOS transistor is series-connected to a resistance load. This level converter inverts a logic signal input to the IN terminal with the amplitude of the VHT voltage, and outputs the inverted signal to the OUT terminal.
The arrangement shown in FIG. 16 can reduce the number of elements, compared to the conventional level converter. However, the power supply current always keeps flowing via the resistor and NMOS transistor in a case where a high-level logic signal is input (a low-level logic signal is output).
In a recent printhead in which many nozzles and switching elements are arranged at high density, even a slight increase in current consumption per nozzle (heater) leads to a large current as a whole, raising the head temperature. Particularly, the temperature rise of the head seriously influences discharge characteristics, degrading the print quality.